# [sdiy] SSM2164 Phaser - another way?

Mattias Rickardsson mr at analogue.org
Fri Feb 21 13:55:39 CET 2014

```On 21 February 2014 07:07, David G Dixon <dixon at mail.ubc.ca> wrote:
> From my understanding, the 2164 likes up to 20V peak-to-peak input signals
> without clipping.  My understanding was that the 2164 would start to clip
> with input currents above about 330 uA.  That's the number I design all my
> 2164 circuits around.

Didn't you forget a square root of 2 there?

If 0 dBu = 0.775 V rms, this corresponds to a 1.1 V peak sinewave
(root of 2 larger). With a 30k input resistor this means a sweetspot
input current of 37 uA peak. Clipping is around 22 dB above this,
which means 460 uA. Your 330 uA is root-of-2 smaller.

I usually memorize the number 37 microampere for the nominal input
current, and count with 20 dB headroom above that instead of 22. Since
20 dB is a factor of ten, from 37 we get 370 microampere which I take
as the level to keep myself below in the designs. (I hope those extra
40 uA give a bit more mojo.) ;-)

> From: Donald Tillman [mailto:don at till.com]
> On Feb 20, 2014, at 5:29 AM, Neil Johnson wrote:
> > David G Dixon  wrote:
> >> The 2164 does develop a measureable voltage on its input terminals
> >> when the gain is increased (I've measured it).  It is not
> large, but
> >> will create some error if the design absolutely depends on
> >> that voltage being exactly zero.
> >
> > Which is probably most designs using a fixed resistor for the
> > V-to-I conversion.  This voltage will cause distortion since the
> > simple linear relationship between Vin and Iin no longer holds.
>
> I don't understand what you're saying here.

That the voltage on the input varies unlinearly with the input
current, and that the input current through the input resistor
therefore gets a distortion since it's not equal to the ideal U/R but
rather (U-Uin)/R where Uin varies.

/mr
```