[sdiy] Op amp clips prematurely?
nitro2k01 at gmail.com
Sun Feb 2 21:00:27 CET 2014
On 2 February 2014 19:33, <nvawter at media.mit.edu> wrote:
> However, I was greatly surprised when I began testing my circuit. I haven't
> attached it to the micro yet. Simply looking with a scope at the op-amp
> output has shown me a serious issue (4). While the bottom end of the range
> produces the expected one-to-one linearity, it appears as if there's a
> discontinuity where the input range 2.8V to 3.3V all maps to 3.3V. To make
> that diagram, I connected a 20k pot as a voltage divider to the input of the
> op-amp buffer circuit and that's the result of turning it CW then CCW. BTW,
> the scale is 1 V/seg and 1 sec/seg.
> I get the same result from a different MCP607 chip (same shipment). I also
> get the same result driving it from a 50k pot as well as from the membrane
> potentiometer, too. The spec for the MCP607 says the rail-to-rail extends
> to about 50mV at either end of the scale, which would be fine for my
> application but this is much further than that.
> So, is there something fundamental that I'm missing? Is this the proper
> op-amp for the task? Is there something in the datasheet that would
> indicate to me that it's not well-suited for this task? Or another
> recommendation for an op-amp? Thank you very much for any
Yes, there's something in the datasheet to suggest that. Reading the
MCP607 'sheet you linked, it specifies:
Common Mode Input Range Min: VSS – 0.3 V Max: VDD – 1.1 V.
On the other hand, the input range actually goes slightly below Vss,
(the negative rail) but doesn't reach the positive rail.
Whereas "Linear Output Voltage Range" is specified as 50 mV inside the range.
In other words, the output is rail to rail, whereas the inputs aren't
quite. This make perfect sense in many uses for an opamp, such as when
amplifying a signal. This is, as a certain Australian video blogger
would put it, a trap for young players.
One way to solve your problem would be to connect the pot's connection
to the positive rail in series with a 50k resistor (or generally
speaking, identical to the pot's value.) Then you connect the opamp in
a non-inverting amplifier configuration with gain 2, as described in
You want the values to be identical which gives a gain of 2.
Now, since the pot forms a voltage divider that halves with the
resistor, this will produce at most Vdd/2 V on the positive input.
Since the two resistors in the feedback loop also form a divider, as
seen by the negative input, the negative input will see at most Vdd/2,
even if the output is pretty much at Vdd. Wire it up and see for
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