[sdiy] $53 Intel Edison dual 500MHz Atom 1GB RAM SOC board has I2S + Intel Xeon Phi 72 core . . .

[Robin Whittle]

If Intel hasn't verified the hardware implementation of the I2S
interface, then they can't have tested this interface in the current
production devices.  I guess one would have to be unlucky to get a
device with a dud I2S interface.


Searching for "edison module hardware guide" turns up a later version
002 than the 001 I linked to in my previous message.  The home of this
document is - in whatever its current version it is up to:

  https://communities.intel.com/docs/DOC-23158

It is still from September 2014, and the I2S material seems to be the
same.  This document states that the Atom CPU is 32 bits (IA-32):

   The SoC contains dual IA-32 cores operating at 500 MHz.  The
   architecture includes 2-wide instruction decode and Out Of Order
   Execution with 1 MB cache shared between the two CPU cores. It
   includes Intel SIMD Extensions 2, 3, 4 (SSE2, SSE3, SSE4.1/4.2).

but I thought it was 64 bits.   According to:

  http://en.wikipedia.org/wiki/Intel_Atom_%28CPU%29

not all Atom CPUs can run 64 bit code.  This article, which only
mentions the Edison once:

  http://en.wikipedia.org/wiki/Atom_%28system_on_chip%29

lists the Silvermont cores as all being 64 bit.  I couldn't easily find
anything which confirms the Atom cores can run 64 bit code.


This page reports that the current consumption rises to 500mA with a
"lot of number crunching and blasting bits out of the radios".  If that
is at the maximum input voltage of 4.5 volts then this is just over 2
watts, so I think the package would require cooling.

  - Robin