[sdiy] $53 Intel Edison dual 500MHz Atom 1GB RAM SOC board has I2S + Intel Xeon Phi 72 core . . .

Robin Whittle rw at firstpr.com.au
Thu Dec 4 03:35:20 CET 2014

I am replying to Brian and nvawter.  I also look at Atom Silvermont
floating point performance.  This CPU will be in the next generation 72
core Intel Phi.

Brian, the TI DSP chip and devboard you mention:


looks good to me for what it is, but I was interested in the Edison
because of the possibility of writing sound and music code in C++, with
full floating point processing.  This range of Intel DSPs is 16 bit
integer only, which is a totally different thing.

nvawter, I can understand the attraction of sharing patches etc. via the
Net.  However, having anything connected to the Internet raises problems
with security, privacy, robustness against viruses, worms etc. and the
need for updating the kernel and other programs and parts of the OS in
order to keep the system secure.  Managing such things is likely to be
beyond the capabilities or interests of most users.

Some indication of the Intel Edison power consumption can be found at:


    8.2 volts 120mA when the system boots.  I guess this was with the
    mini breakout board.


    This reports "under 1 watt", with the mini breakout board, but I am
    not sure if this is with both cores running flat out with floating
    point math.  I guess that is measured at the 3.3V to 4.5V input,
    which translates approximately into "under 300mA".

    The CPU performance of the Edison is way beyond that of the
    Rasberry Pi (ARMV6k 700MHz) and Beagleboard Black (ARM Cortex-A8
    1GHz).  This is using a benchmark:


    which doesn't mention floating point.

Some more sysbench results, including comparison with a Core2Duo PC
(I guess at 1.4GHz):


Some information (with no reference given - I don't trust it) on
floating point performance of various CPU types, including 3 types of
Atom as if they were the same, which I recall is not the case:


This fellow reports on the Intel Edison running as a Linux system,
complete with GCC.  He wired five of them up to be a WiFi connected
cluster . . . but it is not clear that he did anything meaningful with
them.  His interest, in part, is power and purchase cost of computing,
comparing it to renting a virtual server.  He shows how to solder 4.5V
power wires to the Intel Edison itself, without the need for connectors
or breakout board.


On floating point performance:


   The FPU - one per core, I assume - is reported to be about twice as
   fast as the Atom CPUs of ~2008.  This article also states that the
   Silvermont design was "co-optimized" with the development of the
   22nm process.  This would be for leakage and speed, as mentioned

Physical size of the Tangier SoC chip.  The 12" wafers apparently cost
$2.7k each:


The Quark is a 32 bit Pentium-like CPU running at 100MHz, but it is not
yet usable with current software:



Agner Fog's 205 page, amazingly detailed and up-to-date document on
internal architecture of various CPUs, including the Silvermont.


Pages 153 and 153 have the floating point timing by clock cycles - 1
clock cycle for single precision FP multiply and add, with 3 clock
cycles latency.  I guess other types of CPU core can't be any faster per
clock cycle, but they might have more capacity to process FP
calculations in parallel, especially if they are vectors of operands
suitable for the hardware and the compiler creates suitable
instructions.  (I assume my C++ code won't do this.)

Intel slides from 2013 on the Silvermont architecture, stating that by
early 2014 GCC will be able to optimize its code for this CPU (page 13):


GCC does, since 4.9:


On page 21 it mentions trading off transistor leakage for speed.  For
high speed chips, the leakage is higher.  Page 22 shows that there are
11 metal layers in the interconnect for SoC chips.

More on the transistors:


   The SoC process provides more tuning points in the form of
   lower speed, lower leakage transistors better suited for
   low-power devices. At the same time, it adds the
   high-voltage transistors needed for external I/O. These
   transistors have increased oxide thickness and gate length,
   and they support both 1.8 and 3.3V operation. Also, the
   process can be tweaked to provide a range of density options,
   from 9 to 11 metal layers, at different costs.

The Silvermont core will be part of the next generation (14nm Knights
Landing, late 2015) Intel Xeon Phi - with up to 72 cores (I guess
running at 1 to 2GHz) and in the same package, 16GB of stacked DDR4 RAM



To be followed (maybe in 2017) by a 10nm version Knights Hill, with
integrated Omni-Path interconnect for HPC (High Performance Computing)

The semiconductor and computing juggernaut powers ever-onwards!

  - Robin

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