[sdiy] Integrator output bias question

[ASSI]

On Monday 28 October 2013, 11:39:10, Justin Owen wrote:
> Can anyone explain why the output bias of an op amp integrator might be
> affected by the amplitude of the input waveform?

You might be seeing the effect of miniscule changes of the op-amp input 
current (ideally there'd be none).  Another possibility is that you swing 
too close to the rails where the op-amp loses drive; this will usually be 
more problematic towards the +V rail and keep on accumulating over many 
cycles.

> I've got a single integrator on a breadboard, the input is a +/-5V (10V
> PP) square wave at about 20Hz with a 50/50 mark space ratio. The output
> is a +/- 10V (20V PP) triangle wave - pretty much as expected.
> 
> If I adjust the mark/space ratio of the input square wave, it affects the
> bias upward or downward - which makes sense.
> 
> What doesn't make sense to me is that if I adjust the amplitude of the
> input waveform (possibly below a certain PP voltage?) - that also starts
> to affect the bias of the output waveform. It seems to want to head south
> to the negative rail.

Are you using an op-amp with JFET input perhaps?

> I've since, reproduced similar behaviour in simulation - but I'm still no
> clearer...

As a first measure, have exactly the same impedance from the non-inverting 
input to ground than you have between the integrator input and the inverting 
input of the op-amp.  Also, keep that impedance as low as possible (that 
means make the cap larger for the same time constant, which comes with its 
own set of problems).


Regards,
Achim.
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