[sdiy] Integrator output bias question

[Justin Owen]

-----Original Message-----
From: Veronica Merryfield [veronica at merryfield.ca]

> Can you post the circuit? My suspicion is that you have not matched the input impedances.  

Sure...

I started with this: http://www.sdiy.org/juz/I_01a.png - pretty much every combo I tried, the output waveform of the active integrator wanted to head south.

I got to this: http://www.sdiy.org/juz/I_02a.png - which is what I have here on my breadboard.

The behaviour of the second sim and my bboard are similar - changing the input amplitude changes the output bias.

Thanks!






On Oct 28, 2013, at 11:39 AM, Justin Owen <juzowen at gmail.com> wrote:

> Can anyone explain why the output bias of an op amp integrator might be affected by the amplitude of the input waveform?
>  
> I've got a single integrator on a breadboard, the input is a +/-5V (10V PP) square wave at about 20Hz with a 50/50 mark space ratio. The output is a +/- 10V (20V PP) triangle wave - pretty much as expected.
>  
> If I adjust the mark/space ratio of the input square wave, it affects the bias upward or downward - which makes sense.
>  
> What doesn't make sense to me is that if I adjust the amplitude of the input waveform (possibly below a certain PP voltage?) - that also starts to affect the bias of the output waveform. It seems to want to head south to the negative rail.
>  
> I've since, reproduced similar behaviour in simulation - but I'm still no clearer...
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> What's causing this?
>  
> Thanks.
>  
> Justin
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