[sdiy] Integrator output bias question

[Justin Owen]

Can anyone explain why the output bias of an op amp integrator might be affected by the amplitude of the input waveform?

I've got a single integrator on a breadboard, the input is a +/-5V (10V PP) square wave at about 20Hz with a 50/50 mark space ratio. The output is a +/- 10V (20V PP) triangle wave - pretty much as expected.

If I adjust the mark/space ratio of the input square wave, it affects the bias upward or downward - which makes sense.

What doesn't make sense to me is that if I adjust the amplitude of the input waveform (possibly below a certain PP voltage?) - that also starts to affect the bias of the output waveform. It seems to want to head south to the negative rail.

I've since, reproduced similar behaviour in simulation - but I'm still no clearer...

What's causing this?

Thanks.

Justin