[sdiy] Schmitz ADSR replace pots with CV control?

[cheater00 .]

On Tue, Nov 26, 2013 at 7:16 PM, Tom Wiltshire <tom at electricdruid.net> wrote:

> assuming I did have an envelope that was quantized to a 100KHz clock, how does that generate sidebands in my signal? I don't understand how that process works. I'm talking about an analog envelope that's controlled by uP logic here, not a fully-digital envelope, so there's no quantisation of envelope level, only a small degree of time quantisation. I don't understand how that is supposed to harm the signal.

If a signal has events that are quantised to a clock, the fundamental
of that clock will be present in the signal. This is basic frequency
domain math.

>
> On 26 Nov 2013, at 15:40, "cheater00 ." <cheater00 at gmail.com> wrote:
>
>>> On the PIC, as far as I remember most instructions can take 2-3
>>> cycles. Some more, iirc. Can you write your whole logic in 25
>>> instructions? Because if you go over that, then your envelope will be
>>> hard-synced to a signal slower than 100 kHz, which will definitely be
>>> audible and will carry around with your audio signal. Given that the
>>> envelope is most likely going to amplitude-modulate a signal, side
>>> bands will easily be pushed into the audible range.
>>>
>>> The cheapest FPGAs are around $10.
>>>
>>> Cheers,
>>> D.
>>
>> A cursory glance shows 4 cycles for every instruction, 8 for
>> conditionals, a lot more for maths functions. So those tiny cycles
>> pile up real quick. We're left with probably ~ 10-15 instructions in
>> the loop. And that's still not going to ensure we won't have sidebands
>> leaking into the signal.
>>
>> Yeah, navel-grazing, but there's a good reason to consider worst case
>> scenarios: people will always experiment with synths and push them to
>> their limit.
>
> Sorry, I wasn't clear. 125ns is the time for a "single cycle" instruction to execute on recent 16F1xxx chips. That's an 8MHz rate. It's true that the instruction cycle is a quarter of the clock speed - that's 32MHz. Since nothing actually runs at the clock rate, the Microchip jargon is mostly to talk about the "instruction cycle" instead. So I've actually got nearer 80 instructions rather than 25, although 25 would probably do it.
>
> I don't believe (but am willing to be convinced) that people will hear because the envelope start/end points are quantised to a 100KHz clock. But the situation isn't even that bad - we might have a delay of 10us after a state change before the envelope reacts, but it'll be quantised at the 8MHz instruction rate, not at the speed of the delay.

That's pretty good. I think 8 MHz isn't going to be audible. I got 100
kHz from thinking about a busyloop with no branching, but an interrupt
handler is indeed going to quantize to those 8 MHz. The only reason
the delay would still be an issue as far as time quantization is if
someone used the envelope as part of a feedback loop. That is, the
envelope triggers something that triggers that envelope again. The
minimum processing delay will show itself then. You could parametrize
it and bring it out to the front panel, on the one hand giving people
a tangible cue that the delay's never going to be 0, on the other hand
allowing synthesis methods like Karplus-Strong, delays, sequencers,
etc.

One issue left is that at a 100 kHz triggering rate you're only
looking at a 10 msec attack, and that's going to again change how
things sound because even if this frequency is inaudible, it's going
to push inaudible noise into the audio band in the VCA.

However I am not of the opinion you can easily fit the envelope logic
in 25 cycles. Because of the state transition lag, you'll have to
deglitch the envelope logic. I believe that if state transitions are
faster (on the order of gate propagation delay) this can be skipped,
but now you're talking about really slow transitions, so your envelope
needs to really be sure it wants to change its state before it does
so.

I wonder what of the above is apparent with the PIC based envelope
generator someone posted above. Has anyone got one of those? Can you
run tests like the above? 1) an env in a feedback loop, with the
shortest attack and decay and no sustain or release - what frequency
of oscillation do you get? 2) put white noise through a low pass
filter, and through a VCA which is in turn controlled by an envelope
with the lowest ADSR settings you can get (as in 1). Use the output of
that to drive the PIC based envelope with AD set to 0, sustain at 50%,
release at 0. Does the envelope glitch out?

I'm still of the opinion that a tiny FPGA could be a better idea. They
don't cost more. And you aren't venturing onto thin ice with little
theoretical basis like you do with microprocessor control, since
you're again working with gates.

Cheers,
D.