[sdiy] Schmitz ADSR replace pots with CV control?

[Tom Wiltshire]

On 26 Nov 2013, at 15:40, "cheater00 ." <cheater00 at gmail.com> wrote:

>> On the PIC, as far as I remember most instructions can take 2-3
>> cycles. Some more, iirc. Can you write your whole logic in 25
>> instructions? Because if you go over that, then your envelope will be
>> hard-synced to a signal slower than 100 kHz, which will definitely be
>> audible and will carry around with your audio signal. Given that the
>> envelope is most likely going to amplitude-modulate a signal, side
>> bands will easily be pushed into the audible range.
>> 
>> The cheapest FPGAs are around $10.
>> 
>> Cheers,
>> D.
> 
> A cursory glance shows 4 cycles for every instruction, 8 for
> conditionals, a lot more for maths functions. So those tiny cycles
> pile up real quick. We're left with probably ~ 10-15 instructions in
> the loop. And that's still not going to ensure we won't have sidebands
> leaking into the signal.
> 
> Yeah, navel-grazing, but there's a good reason to consider worst case
> scenarios: people will always experiment with synths and push them to
> their limit.

Sorry, I wasn't clear. 125ns is the time for a "single cycle" instruction to execute on recent 16F1xxx chips. That's an 8MHz rate. It's true that the instruction cycle is a quarter of the clock speed - that's 32MHz. Since nothing actually runs at the clock rate, the Microchip jargon is mostly to talk about the "instruction cycle" instead. So I've actually got nearer 80 instructions rather than 25, although 25 would probably do it.

I don't believe (but am willing to be convinced) that people will hear because the envelope start/end points are quantised to a 100KHz clock. But the situation isn't even that bad - we might have a delay of 10us after a state change before the envelope reacts, but it'll be quantised at the 8MHz instruction rate, not at the speed of the delay.

Finally, assuming I did have an envelope that was quantized to a 100KHz clock, how does that generate sidebands in my signal? I don't understand how that process works. I'm talking about an analog envelope that's controlled by uP logic here, not a fully-digital envelope, so there's no quantisation of envelope level, only a small degree of time quantisation. I don't understand how that is supposed to harm the signal. I could have a series of analog envelopes that just so happen to occur at 0.00001 secs, 2.40001 secs and 3.15002 secs - they'd be "quantized" to a 100KHz clock too. Do they cause the same sidebands? If not, why not, when I could make an identical signal with my digital-logic envelope?

T.