[sdiy] Schmitz ADSR replace pots with CV control?

[cheater00 .]

> On the PIC, as far as I remember most instructions can take 2-3
> cycles. Some more, iirc. Can you write your whole logic in 25
> instructions? Because if you go over that, then your envelope will be
> hard-synced to a signal slower than 100 kHz, which will definitely be
> audible and will carry around with your audio signal. Given that the
> envelope is most likely going to amplitude-modulate a signal, side
> bands will easily be pushed into the audible range.
>
> The cheapest FPGAs are around $10.
>
> Cheers,
> D.

A cursory glance shows 4 cycles for every instruction, 8 for
conditionals, a lot more for maths functions. So those tiny cycles
pile up real quick. We're left with probably ~ 10-15 instructions in
the loop. And that's still not going to ensure we won't have sidebands
leaking into the signal.

Yeah, navel-grazing, but there's a good reason to consider worst case
scenarios: people will always experiment with synths and push them to
their limit.

D.