[sdiy] Bus for digital patching of synths

[cheater00 .]

On Sat, Nov 9, 2013 at 3:50 PM, Rainer Buchty <rainer at buchty.net> wrote:
> On Fri, 8 Nov 2013, cheater00 . wrote:
>
>> On Fri, Nov 8, 2013 at 2:45 PM,  <rburnett at richieburnett.co.uk> wrote:
>>>
>>> I think Paul Maddox played about with the idea of a digital modular synth
>>> some time ago, (appologies if my memory serves me badly!)
>>
>>
>> I think I've never heard of this. Has anyone more on this topic?
>
>
> That was the OpenSynth idea. Not sure if the mailing list archives still
> exist, but I have an mbox file somewhere.
>
> The crux pretty much was the digital bus where each module would put its
> data so that any input could pick it up based on the given patch
> configuration.
>
> This is where sheer size and according scalability issues arise. You have $m
> modules with $o outputs each who want to place their data on the bus. Sounds
> like time-slice? Yes, but you would need to have sufficiently high data
> rates then to support the bandwith requirements of m*o*sizeof(audio word in
> bits)*sample frequency Bit/s
>
> Each output alone will require at least 48kHz*16 Bits which is already
> 768kBit/s (96 kByte/s, SI kBytes that is, not kibibytes). If you want to go
> 24bit/192kHz (and for the sake of "state of the art in studio technology",
> audiophiles, and whatnot we want), then it's even 576kBytes/s, which is
> roughly 5MBit/s.
>
> This was just *one* output. We have $m of those.
>
> A single VCO with individual saw, tri, and square outputs would therefore
> already require around ~15MBit/s raw data rate. Each VCO's waveform should
> have its assigned VCA for waveform mixing (+3*5MBit/s for VCA outputs)
> feeding a summer (+5MBit/s for summer output if we assume that the VCF only
> has one, not 3 inputs) which outputs the waveform mix to the state-variable
> VCF (+3*5MBit/s for VCF output: LP, BP, HP), each output feeding again an
> individual VCA plus summer (+20MBit/s), finally feeding the final VCA
> (+5MBit/s for VCA output).
>
> 12*5MBit/s=60MBit/s so far and we don't have any modulation yet.
>
> You want individual envelopes for all (7) VCAs? add 35MBit/s.
> You want individual envelopes for pitch and filter frequency? add 10MBit/s
>
> LFOs, too? Well, double those 45MBit/s above for ultimate flexibility.
>
> Makes 150MBit/s already for this single-osc, single-voice setup (or around
> 100MBit/s if we go for a lesser modulation-friendly approach) and we haven't
> even touched protocol overhead (probably neglectable, as it is basically a
> couple of bytes of source address per module output and eventually an extra
> slot for configuration data), safety overhead for some FEC and checksumming
> (better drop one audio packet than play a defective one), and eventual
> issues arising from the modules detecting when it's time to put their own
> data onto the shared bus.
>
> So skip the shared bus and go for a central crossbar chip.

Yeah until I read the last sentence I wasn't not sure why you
described the above in such great lenghty detail, obviously having a
single collision domain shared by a huge amount of transceivers is a
bad idea.

> That puts less
> stress on the individual patchcord (which just needs to serve those
> ~5MBit/s), but of course moves the problem as you then need a capable
> crossbar which should be able to handle at least something in the GBit/s
> area.
>
> Possible? Today, yes. A Virtex 7 offers 96 transceivers of sufficient
> throughput and enough logic to build a fast enough crossbar.
>
> Back then, i.e. around a decade ago, quite impossible.

Yeah, it looks like there's no common standard supporting fast
synchronous data transfers in finely-grained TDM, so likely no silicon
that one might want to buy either. FPGA might be very good for that
purpose because very little logic needs to happen - in fact, given
that we only have very few new links being established and old ones
being deestablished, it's probably a good idea to have a companion
chip which modifies the FPGA code and uploads it. I know people do
stuff like that, I wonder how difficult it can become. We're talking
about very simple stuff, literally "connect input X at time division Y
to output Z"

Cheers,
D.