[sdiy] Logic Gate help (Help!)

[ASSI]

> all the inputs or
> or the outputs from the first two gates and the ouput of the second (NOR
> together a NAND and OR of the same inputs).

Nonsense, should have written the truth tables down first.  So, going from 
the canonical implementation of an equivalence gate, making a NOR out of 
that last OR makes it an XOR, the rest is wrong.

Inverting all the inputs does nothing interesting of course: it makes a NOR 
out of the AND and an AND out of the NOR and we are left at the start since 
these see the same inputs.  But you can push the inversion at the output one 
stage earlier, that makes the output gate an AND and the the gates at the 
input NAND and OR.

But in RTL NOR are easiest, so the implementation using two NOR is better, 
leaving you to find a way to implement an AND.


Regards,
Achim.
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