[sdiy] Static ADC and DAC recommendations?

[Neil Johnson]

cheater cheater wrote:
> Wait a sec guys - I thought the usual approach was folding
> converters. That is, you take the input signal, scale it to e.g.
> 0-1V, and see if it's the upper or lower half (so if it's positive
> then negative). You call that the msb, deduce 0.5V*logical value
> from the original signal, and you get something ranges from 0 to
> 0.5V. Then you scale that up twice to get a range 0-1V again, and
> repeat the whole process, getting the second bit, and so on. Only 8
> comparators here, and, eh, how many transistors? I don't know off
> the top of my head. Why would that be so expensive to make in
> silicon?

It sounds like you're talking about successive-approximation, in which 
case you need a clock.

Or if a non-clocked circuit you'll have such a long chain of 
comparators, amplifiers and subtractors that the delay between the MSB 
decision and the LSB decision will be very long.  Plus the fact that 
you're having to implement precise gains at every stage otherwise 
performance suffers, especially at the LSB end which is where it matters 
most.

I think the closest I've seen to what you describe is used in bench-top 
HP/Agilent DMMs, where they process the input sample using multiple 
dual-slope integrations to get to 8-digit performance.  But that is a 
slow process, although you can skip the later stages for faster update 
rate at the cost of fewer digits.

>> If you do want a clockless converter, John Simonton wrote an
>> article in a long past polyphony on how to do this with LM339's
>> However while one LM339 will give you a 4 bit converter
>
> I believe that's exactly what he's doing. I looked at doing this sort
> of thing with an LM339, but I just can't believe there isn't a chip
> out there that does this in integrated form. It seems like a
> no-brainer. I hope someone has a lead on that.. I *would* expect this
> sort of thing to be viewed as an anachronism nowadays, though, and
> probably limited to NOS or small-yield production runs.

Trouble with the non-clocked approach is that you never really know when
the output is valid.  With a clocked converter you know precisely when
you have a valid output, and how that relates to the input at some time 
in the past.

Neil
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