[sdiy] Logic Gate help (Help!)

ASSI Stromeko at nexgo.de
Wed Jan 23 19:52:48 CET 2013

On Wednesday 23 January 2013, 16:26:11, Justin Owen wrote:
> I'm looking to build a 2x input OR Gate and a 3x input XOR Gate using
> Resistor/(NPN)Transistor Logic.

Are you doing some repair on the Apollo computer?

> I have this schem of a 3x Input NOR:
> http://en.wikipedia.org/wiki/File:RTL_3-Input_NOR_Gate.svg
> 1) From that schem, if I remove 1x Input and either Invert the output or
> take the Q Output from the joined Emitters - does that give me a 2x Input
> OR?

Yes.  A 2-input NOR is a 3-input NOR with the third input tied low and it's 
easy to see that the third resistor/transistor becomes superfluous in this 

> 2) Is a 3x Input NOR the same as an XNOR? i.e. If I invert the output of
> that schem I get a 3x Input XOR from that XNOR? The truth tables suggests
> not - but I'm asking anyway.

No. XNOR is otherwise known as "equivalence", the canonical implementation 
is to OR the output of an AND and a NOR of the same inputs together.  To 
make an XOR out of that you can either invert the output, all the inputs or 
the outputs from the first two gates and the ouput of the second (NOR 
together a NAND and OR of the same inputs).  

> If not! Anyone got any pointers to a 2x In OR and a 3x In XOR using RTL?

De Morgan's law will help you.

+<[Q+ Matrix-12 WAVE#46+305 Neuron microQkb Andromeda XTk Blofeld]>+

SD adaptation for Waldorf Blofeld V1.15B11:

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