[sdiy] Logic Gate help (Help!)
don at till.com
Wed Jan 23 18:37:07 CET 2013
On Jan 23, 2013, at 8:26 AM, Justin Owen <juzowen at gmail.com> wrote:
> I'm looking to build a 2x input OR Gate and a 3x input XOR Gate using Resistor/(NPN)Transistor Logic.
That's not a request that comes up very often. :-)
> I have this schem of a 3x Input NOR: http://en.wikipedia.org/wiki/File:RTL_3-Input_NOR_Gate.svg
> 1) From that schem, if I remove 1x Input and either Invert the output or take the Q Output from the joined Emitters - does that give me a 2x Input OR?
Yes to the first part. Don't take the output from the emitters. The inverter stage will be a single transistor version of that schematic.
> 2) Is a 3x Input NOR the same as an XNOR? i.e. If I invert the output of that schem I get a 3x Input XOR from that XNOR? The truth tables suggests not - but I'm asking anyway.
A 3 input NOR is high when all inputs are low.
An XNOR is an XOR with an inverted output.
A three input XOR is high for an odd number of high inputs.
A three input XNOR is high for an even number of high inputs.
> Anyone got any pointers to a 2x In OR and a 3x In XOR using RTL?
For the 2 input OR, just invert the NOR output like you planned above.
A three input XOR is a little more complicated. You'll need three separate sections.
* The third section is a single 4 input NOR gate. It's output will be low when any of its inputs is high.
* The second section is four 3 input NOR gates, each goes high when it detects a combination of even high XOR inputs.
* The first section is three inverters providing inverted versions of all three inputs for the second section.
The rest is left as an exerciser to the reader.
Palo Alto, California
don at till.com
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