[sdiy] dsPIC Parallel Master Port (PMP) - DRAM for reverb memory etc.

[Tom Wiltshire]

Robin, Richie,

Thanks both.

You're dead right that the fundamental problem is the large number of pins required. For fast memory access, that's more or less a given. In that parallel will always be quicker than serial, it probably will remain so. The PMP seeks to make life simpler by providing an interface between the dsPIC and the memory which can deal with some of the buffering and timing issues. For example, the hardware can take a 16-bit word and send it as two 8-bit writes on the data bus. This ought to reduce some of the data disassembly and reassembly that Richie mentioned. The hardware also has programmable timing delays so that the code doesn't have to concern itself with those details either. How well this works in practice probably depends heavily on how well the particular chip you're using fits Microchip's idea of how a memory chip behaves.

I wonder whether serial RAM is a feasible solution. Microchip themselves have 128K x 8bit chips available, and connecting a pair (or even a quad) of those wouldn't use half so many pins as a fully parallel set up. There'd still be some faffing about setting data up for storage and reassembling it after storage, but that seems to be the way things go whatever you do. Running the serial (SPI) bus at 10MHz would give you plenty of bandwidth above what you'd need for audio, although there'd still be a need to be as efficient as possible, and if access was required to many different individual samples at once, time might become a problem again.

Still, I think it's worth an experiment.

Thanks,
Tom


On 9 Aug 2013, at 13:38, rburnett at richieburnett.co.uk wrote:

>> The best idea I came up with, which I have never tried, is to use a
>> 1,048,576 x 8 bit EDO (Extended Data Out) Dynamic RAM....
> 
> Hi Robin,
> 
> I have tried this in practice and managed to tag up to 32MB of EDO RAM onto a dsPIC30f6014 device a few years ago.  It worked fine, but the memory bandwidth wasn't particularly impressive due to all of the bit-bashing for the various row/col address setup/hold times, CAS/RAS strobing etc.  This is particularly so if you want to access the memory in 24-bit wide words over just an 8-bit wide data bus.  You spend a lot of time splitting all of the reads and writes into high, mid and low bytes and reassembling the data which really slows things down.  So, although it worked great for a basic 24-bit stereo audio delay, it wasn't up to implementing something like polyphonic sample playback or a decent reverb algorithm.
> 
> Other observations were that DRAM timing diagrams can be a bit intimidating and complex to figure out at first, and that fast DRAM chips like those found on old computer SIMMs are *VERY* sensitive to signal integrity issues on the digital lines.  I had to wire the DRAM chip to the dsPIC pins directly with 25mm long wires for prototyping.  The 70mm PCB traces from the dsPIC to the expansion connector on the dsPICDem development board were already way too long!  Although you can not clock your dsPIC into the 100's of MHz, the I/O lines still change state in a few nanoseconds and the fast DRAM chip can easily see signal reflections from poor termination as double clocking!  This is what I spent the majority of the time sorting out with a fast oscilloscope.  So if you ever try this, use the absolute shortest most direct wiring from the outset to avoid a lot of head-scratching!  Or if you decide to use several instances of 80's PC SIMMs you'll probably need to look at terminating the end of the PCB traces to control signal reflections.
> 
> -Richie,
> 
> 
>  For instance
>> this device or any of those which have the same pinout and timing:
>>  http://www.digchip.com/datasheets/parts/datasheet/308/V53C808H35.php
>> These are 5 volt chips in 28 pin SOJ or perhaps TSOP packages.  They
>> have been obsolete for at least ten years.  This datasheet is from 1998.
>> They are 5 volt DRAMs with these pins:
>>   10 address pins - the address is clocked into the device in two
>>   sets of 10 bits, by the next two pins:
>>   /RAS  Row Address Strobe
>>   /CAS  Column Address Strobe
>>   /OE Output enable
>>   /WE Write enable
>>    8 data input/output pins
>> I can't remember the details but I thought it might be feasible to drive
>> A0 to A7 parallelled to D0 to D7 and to drive A8 and A9 separately.  If
>> A8 and A9 were not used, then this would be 64k bytes of memory.  With
>> these two bits used, giving four more address bits, the capacity would
>> be 256k bytes.
>> I am not sure to what extent the PMP (Parallel Master Port) would be
>> useful in such a scheme.
>> The trouble is that by the time this many pins are used, after the DAC
>> pins are accounted for, there's not much left.  This might make more
>> sense with a larger pin-count dsPIC.
>>  - Robin
> _______________________________________________
> Synth-diy mailing list
> Synth-diy at dropmix.xs4all.nl
> http://dropmix.xs4all.nl/mailman/listinfo/synth-diy