[sdiy] dsPIC Parallel Master Port (PMP) - DRAM for reverb memory etc.

[Robin Whittle]

A few years ago I researched ways of attaching RAM to a dsPIC -
specifically a 28 pin DIP one with an internal stereo audio DAC.  The
aim was to provide reasonably fast access to make extended reverb or
delay memory.

The trouble with SRAM is that there are very large numbers of address
pins, plus the data pins, and the packages are large.

The best idea I came up with, which I have never tried, is to use a
1,048,576 x 8 bit EDO (Extended Data Out) Dynamic RAM.  For instance
this device or any of those which have the same pinout and timing:

  http://www.digchip.com/datasheets/parts/datasheet/308/V53C808H35.php

These are 5 volt chips in 28 pin SOJ or perhaps TSOP packages.  They
have been obsolete for at least ten years.  This datasheet is from 1998.
 They are 5 volt DRAMs with these pins:

   10 address pins - the address is clocked into the device in two
   sets of 10 bits, by the next two pins:

   /RAS  Row Address Strobe
   /CAS  Column Address Strobe

   /OE Output enable
   /WE Write enable

    8 data input/output pins

I can't remember the details but I thought it might be feasible to drive
A0 to A7 parallelled to D0 to D7 and to drive A8 and A9 separately.  If
A8 and A9 were not used, then this would be 64k bytes of memory.  With
these two bits used, giving four more address bits, the capacity would
be 256k bytes.

I am not sure to what extent the PMP (Parallel Master Port) would be
useful in such a scheme.

The trouble is that by the time this many pins are used, after the DAC
pins are accounted for, there's not much left.  This might make more
sense with a larger pin-count dsPIC.

  - Robin