[sdiy] 1 bit serial stream delay approaches..

[Martin Klang]

In the shift-register scenario, to make the most of your available memory you'd want to use a single bit to indicate HIGH.
Write the input gate state to one bit index, and read it from another, the difference being your delay time.

Increment both indices and repeat on the next timer interrupt.
You increase the delay time by increasing the offset to the read index and/or the timer period.

Did I get that right?

/m

On 24 Sep 2012, at 16:33, Jean-Pierre Desrochers wrote:

> 
> The GATE *events* could be like the following:
> ON....OFF...........ON.OFF............ON.............................OFF...
> all produced in a short period of time (for example < 500msec.)
> and delayed of 3 sec for example again.
> That's why the *shift register* approach should be able to register all these
> so called events without missing one.
> JP