[sdiy] 1 bit serial stream delay approaches..

[Jean-Pierre Desrochers]

The GATE *events* could be like the following:
ON....OFF...........ON.OFF............ON.............................OFF...
all produced in a short period of time (for example < 500msec.)
and delayed of 3 sec for example again.
That's why the *shift register* approach should be able to register all these
so called events without missing one.
JP


 On Mon 24/09/12 12:26 , Ingo Debus igg.debus at t-online.de sent:
> 
> Am 24.09.2012 um 15:01 schrieb Olivier Gillet:
> 
> > Since the variation of delays might alter the
> order of events, you> might have to insert the event somewhere in the
> middle of the list,> which requires O(log n) operations if the event
> list is kept sorted> (and not O(n) as stated).
> 
> But what kind of events are we talking here? I think the original question
> was about delaying a gate signal, so the possible events would be
> "gate goes high" and "gate goes low". If the order of
> these gets altered, we'll end up in a mess, won't we?
> "A 555 oscillator has so much jitter that sometimes the second pulse
> comes before the first one" (I think it was Walt Jung who said
> that).
> Ingo
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