[sdiy] 1 bit serial stream delay approaches..

[Tom Wiltshire]

Sounds to me like you're over-thinking this, unless I'm missing something. I don't see any problem with voltage-control of delay time, either way you implement it.

You store the time that an event arrived in the queue. The output pointer moves through the queue to each event in order and if enough delay time has passed (e.g. if current time >= event time + delay), it outputs it and moves to the next event. What counts as "enough delay time" can be modulated without affecting the order, just as it would be with a BBD. Since the incoming events are already in the right order to be sent out, there's no need to sort them.

Regards,
Tom

On 24 Sep 2012, at 13:04, Martin Klang wrote:

> 
> Bear in mind that a nice, simple, constant time FIFO only works if the output events are in the same order as the input events, ie you have a fixed delay time.
> 
> If the delay is variable (voltage controlled, anyone?) then you will need either a sorted list (adds O(n) at insertion time) or to loop through every queued event in your timer interrupt. Either way, it adds cycles which will limit the performance of the delay.
> 
> I guess the RAM-as-shift-register approach can be seen as a direct-indexed sequencer, where the memory address represents time. The (big!) advantage is constant read and write times. Disadvantage is a very very sparse data store, whose size becomes the main performance limiting factor.
> 
> best,
> 
> /m
> 
> On 19 Sep 2012, at 18:07, Tom Wiltshire wrote:
> 
>> 
>> On 19 Sep 2012, at 16:11, Olivier Gillet wrote:
>> 
>>>> Would I'd probably do: a micro controller, use a 16 bit timer as a
>>>> quasi-realtime clock, and a sequencer-like event FIFO. Each input edge
>>>> writes a timestamped event record into the fifo, and a read routine
>>>> calculates the out event times, and generates the output signal when
>>>> that time has come.
>>> 
>>> I would have done that too. The advantage of this solution is that it
>>> can allow very long delay times - the SRAM of the chip only constrains
>>> the maximum simultaneous number of events traveling through the delay
>>> line. If you use a 50kHz time base as your realtime clock, you could
>>> use 23 bits timestamps (the highest bit storing whether the event is a
>>> raising or falling edge), giving a maximum delay time of 167 seconds.
>>> With 1 kbyte of SRAM (roughly what the low-end PICs / AVRs have), this
>>> allows ~300 events at a time to travel through the delay.
>> 
>> I'll put another vote in for this technique.
>> 
>> It separates the timing resolution from the RAM size. If you use a circular buffer to make an actual delay line, then the better the timing resolution, the shorter the delay. If you go with a sequencer-style solution, the RAM only dertermines the maximum *number* of events, not the timing resolution. Consequently you can get better resolution with longer delays from a smaller chip - a much better solution in my view.
>> 
>> Tom
>> 
>> 
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>