[sdiy] cs4344 DAC output stage

[James J. Clark]

On Thu, 20 Sep 2012, Richie Burnett wrote:

> Hi Jim,
>
> Thanks for taking the time to reply to my question.  Are you using your 
>CS4344
> part in "Internal SCLK Mode" where the DAC reconstructs its own SCLK 
>(bit
> clock) from your supplied MCLK (master clock) and LRCLK (word clock) 
>signals?
>
> Looking at figure 7 from the CS4344 datasheet, my interpretation is that
> you're only forced to use 16-bit data for each channel when operating in
> "Internal SCLK Mode" with those particular ratios of MCLK/LRCK that you
> mentioned are integer powers of 2.  When you supply the DAC with your 
>own
> external SCLK (bit clock) the data can be up to 24-bits for any of the
> acceptable MCLK/LRCK ratios as far as I can tell.
>
> -Richie,
>


Yes, I use the external SCLK mode. But note that (in section 4.1) SCLK and 
MCLK must be synchronous, by which I understand that SCLK transitions must 
occur on MCLK transitions. This means that the MCLK to SCLK frequency 
ratio must be integers. This rules out having MCLK=24MHz, SR=96 (or 192) 
KHz and bits=24 (48) as that would require MCLK/SCLK=2.667 and SCLK would 
not be synchronous with MCLK.
If you set MCLK to 18.432 MHz it would work out, but I wanted an MCLK of 
24MHz.

Jim