[sdiy] cs4344 DAC output stage

[Richie Burnett]

Hi Jim,

Thanks for taking the time to reply to my question.  Are you using your 
CS4344 part in "Internal SCLK Mode" where the DAC reconstructs its own SCLK 
(bit clock) from your supplied MCLK (master clock) and LRCLK (word clock) 
signals?

Looking at figure 7 from the CS4344 datasheet, my interpretation is that 
you're only forced to use 16-bit data for each channel when operating in 
"Internal SCLK Mode" with those particular ratios of MCLK/LRCK that you 
mentioned are integer powers of 2.  When you supply the DAC with your own 
external SCLK (bit clock) the data can be up to 24-bits for any of the 
acceptable MCLK/LRCK ratios as far as I can tell.

I've always supplied my DACs with the SCLK from the micro as it is generated 
automatically by the serial peripheral interface along with the serial data 
and word clock.  But, I know that you can only use the digital de-emphasis 
function in "Internal SCLK Mode", and it saves having to route the bit clock 
signal from the micro to the DAC too.

Sorry to flog this discussion, but I'm keen to understand potential pitfalls 
before switching my design to a different DAC.

Cheers,

-Richie,



> It's just a matter of math. It seems that the ratio of the MCLK frequency 
> to the SCLK (bit clock) must be a power of 2. So for an OSR (MCLK rate 
> over the LRCLK rate) that is a power of 2 the ratio of SCLK to LRCLK must 
> also be a power of 2 (e.g 32 which only allows 32 bits to be packed in).
>
> Note that although one is only reading in 16 bits in this mode, the DAC is 
> still a 24-bit DAC, and the word is extended by setting the 8 LSBs to 0. 
> So the noise level is that of a 24-bit DAC, but the data is truncated to 
> 16 bits slightly increasing quantization error noise. For an oscillator 
> the signal is usually full-range without too many small signal variations, 
> so you don't really notice a drop from 24 to 16 bits resolution.
>
>
>>
>> I ask because I have a product in the development phase that currently 
>> uses the CS4335 with 24-bit data.  However, this left-justified version 
>> of the CS433x family has just been discontinued and I suspect the rest of 
>> these "large" SOIC-8 variants will follow, so I was thinking of migrating 
>> to the CS4345 part.
>>
>> I've never understood the logic behind delaying the audio data by one bit 
>> in the I2S format, and this quirk can cause problems with some 
>> micros/DSPs. For that reason i've tended to stick with left-justified 
>> data and had no problems, but it seems that I2S format gives you a wider 
>> choice of CODECs.
>
> From the Philips spec:
>
> "The WS line changes one clock period before the MSB is transmitted. This 
> allows the slave transmitter to derive synchronous timing of the serial 
> data that will be set up for transmission. Furthermore, it enables the 
> receiver to store the previous word and clear the input for the next 
> word..."
>
> Hope this clarifies things somewhat!
> Jim
>
>
>
>>
>> -Richie,
>>
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