[sdiy] cs4344 DAC output stage

[Richie Burnett]

> ......One small nitpick is that it is limited to 16 bits when running at 
> 96 or 192KHz with a 128x or 256x OSR (e.g. with a master clock of 
> 24.576MHz).

Hi Jim,

Why does it have to be limited to only 16-bit data for those clock ratios? 
Is it something to do with the I2S format specifically?  or the DAC itself?

I ask because I have a product in the development phase that currently uses 
the CS4335 with 24-bit data.  However, this left-justified version of the 
CS433x family has just been discontinued and I suspect the rest of these 
"large" SOIC-8 variants will follow, so I was thinking of migrating to the 
CS4345 part.

I've never understood the logic behind delaying the audio data by one bit in 
the I2S format, and this quirk can cause problems with some micros/DSPs. 
For that reason i've tended to stick with left-justified data and had no 
problems, but it seems that I2S format gives you a wider choice of CODECs.

-Richie,