[sdiy] 1 bit serial stream delay approaches..

[Olivier Gillet]

> Would I'd probably do: a micro controller, use a 16 bit timer as a
> quasi-realtime clock, and a sequencer-like event FIFO. Each input edge
> writes a timestamped event record into the fifo, and a read routine
> calculates the out event times, and generates the output signal when
> that time has come.

I would have done that too. The advantage of this solution is that it
can allow very long delay times - the SRAM of the chip only constrains
the maximum simultaneous number of events traveling through the delay
line. If you use a 50kHz time base as your realtime clock, you could
use 23 bits timestamps (the highest bit storing whether the event is a
raising or falling edge), giving a maximum delay time of 167 seconds.
With 1 kbyte of SRAM (roughly what the low-end PICs / AVRs have), this
allows ~300 events at a time to travel through the delay.

Olivier