[sdiy] Variable rate waveform playback in NED synclavier

[Scott Nordlund]

> An NCO running at 10MHz sample rate can only change its output every
> 100ns. A common sloppy way to produce a variable-frequency digital
> clock from the NCO is either to generate a clock pulse every time the
> phase accumulator overflows, or to simply take the MSB of the phase
> accumulator to get a "square" wave output. The problem with these are
> that the transitions are quantised to the 100ns master clock period.
> And hence for all output frequencies that aren't exact sub-multiples of
> the clock frequency the output clock waveform jitters between the two
> closest periods. For instance generating a 3MHz clock would result in
> alternating 300ns and 400ns periods. Quite a large period jitter, and
> often with a complex pattern that has a low repetition frequency that's
> audible!

The patent cites 600 ns jitter (which is what they get after delaying the pulses to correct the timing) as being "inaudible" (compared to 2.5 µs for the FM voices). I certainly wouldn't say that's optimal, but it's much better than most other "classic" synths. I mean the ESQ-1 has a sample rate of about 40 kHz...

> In order to remove the jitter, high-performance DDS function generators
> synthesise a sinewave from the NCO using a look-up-table in ROM. (A
> sinewave because it is the only thing you can synthesise digitally over
> the full frequency range without aliasing.) This sampled sinewave is
> then passed through a steep low-pass filter with cutoff at half the NCO
> master clock frequency. This is essentially just a reconstruction
> filter that converts the discrete-time sampled sinewave back to a
> continuous-time sinewave by removing the energy at the image frequencies
> resulting from the sampling process. The resulting smooth sinewave is
> then passed through a conventional level-comparator to turn it back into
> a square wave. The difference is that this square wave was generated
> from the smoothed continuous-time sinewave not directly from the NCO's
> phase accumulator, and it's rising and falling edges are no longer
> quantised to the 100ns master clock period. The period jitter is
> removed and the resulting clock edges are asynchronous to the NCO's
> master clock.
>
> Many modern DDS chips like those from Analog Devices allow you to
> generate variable digital clock signals both ways. The jitter resulting
> from the quick and dirty way is very apparent when comparing the two
> clock outputs side-by-side on an oscilloscope.

I can't see this being applicable to software, but it might be the way to go if anyone wanted to compete with the Fairlight CMI-30A. If anyone wants to start a company, it'll be a fun way to lose a lot of money.