[sdiy] Clock noise problem

[rburnett at richieburnett.co.uk]

> One problem has been persisting ever since I built the synth, and 
> this is some high-pitched
> noise on the audio line and headphone outputs. Today I made several 
> attempts to solve that,
> but I'm a little stuck. Perhaps you could give some advice? With a 
> scope I was able to
> identify the high-pitched noise as the clock frequency used for the 
> memory bank modules (24LC512).

Can you change the software to temporarily stop the clock to the memory 
bank modules to see if the high-pitched noise goes away?  Presumably you 
don't need to be able to read/write to the memory bank all the time the 
synth is playing, just when loading and saving patches?  Even if you 
could just temporarily stop it or change the clock frequency you would 
be able to prove that it is the EEPROM bit clock line that's causing 
your problem.

Out of interest is there a USB connection involved anywhere in yor 
setup?  For example an in-circuit debugger?  Earth loops involving PC 
USB ports can introduce all manner of whistley tones and hisses into 
audio equipment.  It's the high-frequency modern-day equivalent of the 
dreaded 50Hz earth loop!

-Richie,