[sdiy] Variable rate waveform playback in NED synclavier

[Scott Nordlund]

I figured it out. There's no PLL. The M/N notation is explained in patent 4108035, and extended a little in 4345500. It basically looks like a phase accumulator that puts out a clock pulse every time it wraps around. The way they implemented it (M being the "counter increment" and N being the "divisor") just seems to save a few 74xx chips. M and N are fiddled with (and I guess tabularized) to get good pitch resolution and minimal jitter. Basically you put in a high frequency clock and get out a variable rate clock with high frequency resolution and a little bit of jitter, i.e. pretty standard stuff, but it's implemented in an unusual way. Its frequency range should span a little more than an octave (to permit modulation). The third 8 bit bus that goes to the phase register is the phase increment, BUT to avoid (inharmonic) aliasing it's restricted to powers of 2 (as described in patent 4279185). So it's controlling the octave and reducing wavetable resolution by powers of 2 for higher octaves. The wave RAM is 256 bytes, but the waveform can only have 24 harmonics, so you can downsample it by 4 without changing the spectrum. This lowers the image frequencies, but they'd be inaudible at high pitches anyway. And the resolution of the phase modulation isn't reduced either.

 Still reading the patents...