[sdiy] Clock-controlled filters?

[Tom Wiltshire]

On 19 Oct 2012, at 11:01, cheater cheater wrote:

>> 
>> then you'd be looking at using a PLL with a divider to track the input and produce the required HF clock. This is going to be much trickier to make track properly, I'd have thought.
> 
> Not trying to do that. But indulge me - why would I need a divider?

Assume you've got an input frequency F. You're trying to get F x 50, or F x 100, or whatever the filter clock requires. The PLL will track F and produce an output Fout = F. However, if you put a divider (/50) in its feedback loop, it'll try and get the feedback Fout/50 to match F. This requires that Fout = 50 x F.

In short, the divider in the PLL feedback loop allows you to multiply the PLL output frequency. This is commonly done with uP clocks, among *many* other applications.

HTH,
Tom