[sdiy] Fun with LFSRs and such

[Matthew Smith]

Quoth Ove Ridé at 25/03/12 07:41...
...
> The NAND synth consists of four oscillators, where each one acts as a
> gate (starts or stops the oscillation) for the next one. Each
> oscillator is equivalent of a schmitt trigger similar to the on
> pictured here

OK, thanks for that explanation.

...
> And therein lies the problem. The CPLD likely doesn't have schmitt
> inputs, so it will not oscillate in the way God intended.
...

That means I can't do it with the XC95XXX family. BUT, having just done 
a quick Google, from the Xilinx Application Note XAPP382/CoolRunner-II 
CPLDs*:

"The CoolRunner-II CPLD family is the industry’s lowest power 
programmable logic device, operating at a core voltage of 1.8V. It 
provides even lower power consumption than its predecessor, the 
CoolRunner XPLA3 family. More importantly, CoolRunner-II devices are the
industry’s first CPLDs to promote system integration by including 
features such as clock division, DualEDGE, DataGATE, Schmitt trigger 
inputs, I/O banking, and multiple I/O standards."

 From page 8 of said document:

"The Schmitt trigger input voltage threshold is dependent upon the 
output bank voltage. When selected, the Scmitt trigger is designed to 
provide 400 mV of hysteresis when VCCIO is 1.5V,500 mV of hysteresis 
when VCCIO is 1.8V or 2.5V, and 1.0V of hysteresis when VCCIO is 3.3V."

Does that sound like we might be in business? I've been meaning to have 
a play with a CoolRunner so, if so, I'll be putting that on the project 
list right now :-)

Cheers

M

* http://www.xilinx.com/support/documentation/application_notes/xapp382.pdf

-- 
Matthew Smith

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