[sdiy] Idea - Triangle wave DCO core

[jays at aracnet.com]

Tom,

Yes you are right if you know the number of cycles and it is
consistent.

The point that I was trying to make was sometimes it's not always 25
cycles between the interrupt and when it is serviced in a system. It can
vary some depending on how the hardware handles the interrupt and the
software. For example lets say a processor has an instruction that takes
5 cycles and an interrupt happens in the first cycle. You will probably
have to wait the other 4 cycles before handling the interrupt. Now if
that interrupt happens on an instruction that is one cycle then the
interrupt can be serviced on the next cycle. So one is 4 cycles longer
than the other. Another thing that is common is a need for atomic code.
No we aren't going to send the code to Hanford to get it irradiated.
What that means is there maybe several instructions that need to be
grouped together such that an interrupt can not happen when this section
of code is executed. An example would be if you had to touch 4 hardware
registers to do an operation. If you got an interrupt after setting 2 of
them you might not have the hardware setup in the proper state to
program the other 2 when you come back from an interrupt. Normally you'd
turn off interrupts, execute your code and then turn on interrupts. In
this case if the interrupt happens at the beginning of a piece of atomic
code then there can be a large number of cycles before the interrupt is
serviced.

Jay S.

There maybe some atomic code (code that turns off
On Wed, 14 Mar 2012 21:02:40 +0000, Tom Wiltshire
<tom at electricdruid.net> wrote:
> You're right to point it out, but as long as it's a known delay (e.g.
> as long as the interrupt latency is fixed, which it is on some
> processors) you can simply allow for it in the value that you feed to
> the timer. The basic idea is:
> 
> Timer needs to count 3460 cycles. But interrupt latency is 25 cycles.
> So we set the timer for 3435 cycles, which makes the reset pulse
> arrive dead on time.
> 
> Tom
> 
> 
> On 14 Mar 2012, at 20:46, <jays at aracnet.com> wrote:
> 
>> One thing I wonder about here is interrupt latency.
>>
>> I assume that we would run an integrator into a comparator which would
>> generate a signal to reset the integrator via the processor. Normally
>> you'd run that into an interrupt line on the processor. Then the
>> processor would service the interrupt and do the reset. For example
>> depending on the clocking and instructions and interrupt
>> blocking/priorities you could take maybe 10 clock cycles or maybe 20
>> clock cycles before the reset is done. Depending on the processor and
>> clocking that may take ns or it may take us which could affect the
>> frequency.
>>
>> Comments, ideas?
>>
>> Thanks
>> Jay S.
>>
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