[sdiy] Idea - Triangle wave DCO core

[Tom Wiltshire]

You're right to point it out, but as long as it's a known delay (e.g. as long as the interrupt latency is fixed, which it is on some processors) you can simply allow for it in the value that you feed to the timer. The basic idea is:

Timer needs to count 3460 cycles. But interrupt latency is 25 cycles. So we set the timer for 3435 cycles, which makes the reset pulse arrive dead on time.

Tom


On 14 Mar 2012, at 20:46, <jays at aracnet.com> wrote:

> One thing I wonder about here is interrupt latency.
> 
> I assume that we would run an integrator into a comparator which would
> generate a signal to reset the integrator via the processor. Normally
> you'd run that into an interrupt line on the processor. Then the
> processor would service the interrupt and do the reset. For example
> depending on the clocking and instructions and interrupt
> blocking/priorities you could take maybe 10 clock cycles or maybe 20
> clock cycles before the reset is done. Depending on the processor and
> clocking that may take ns or it may take us which could affect the
> frequency.
> 
> Comments, ideas?
> 
> Thanks
> Jay S.
> 
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