[sdiy] Extraneous capacitance?

[Richie Burnett]

> I've got a 78KHz 0-5V pulse signal driving a transistor level shifter. The 
> pulse rise time at the collector is 3.4us, which works out at roughly 47pF 
> of capacitance with the 10K collector resistor.
>
> Where does this capacitance come from? How do I sharpen the pulse edges 
> after passing the signal through the transistor?
> On a similar note, why is the falling edge different?

If your level shifter is a single transistor operating in common-emitter 
mode then there are a few things that might be at work here:

A common-emitter transistor operated as a switch is inclined to go into 
saturation.  Bipolar devices are minority carrier devices and have stored 
charge that must be swept out in order to make them turn off.  Without going 
into detail, the turn-off delay will be longer than the turn-on delay, and 
the collector current may exhibit a slowly decaying "tail" after the main 
turn off.

Even if the transistor could switch off quickly, the rise-time and fall-time 
of the output will be mismatched because the current sourcing ability is 
limited by the passive pull-up (collector resistor.)  A common-emitter 
output stage can sink much more current than it can source, so it is a lot 
better at discharging a capacitive load than it is at charging it.

47pF is not much capacitance at all.  Most likely the sum of transistor 
"Miller" capacitance, wiring/PCB traces, scope probe, cable and scope input 
capacitance.

To improve the performance, use the fastest switching transistor you can 
find, prevent it from going into saturation, reduce the pull-up resistance 
as far as possible, and minimise any capacitive loading at the output (keep 
PCB traces and wiring at this node as short as possible.)  Also make sure 
you're observing the output with a properly compensated x10 oscilloscope 
probe so that you can see what's going on with confidence without loading 
the output.

I hope this helps,

-Richie,