[sdiy] Extraneous capacitance?

[Tom Wiltshire]

Hi all,

I've got a 78KHz 0-5V pulse signal driving a transistor level shifter. The pulse rise time at the collector is 3.4us, which works out at roughly 47pF of capacitance with the 10K collector resistor.

Where does this capacitance come from? How do I sharpen the pulse edges after passing the signal through the transistor?
On a similar note, why is the falling edge different?

Thanks,
Tom