[sdiy] Generating +5V gate signals from +3.3V logic

[Neil Johnson]

Steve Lenham <steve at bendentech.co.uk> wrote:
>
>>>> I'm running a 3.3V dsPIC and I want to generate 0-5V gate
>>>> outputs from it. I've got a 3.3V supply for the uP, and a
>>>> +/-12V for the op-amps, but no +5V supply.
>
>
>>> No idea but I'll seize the occasion to encourage you to use
>>> whatever it takes to make the output voltage stiff and well-
>>> defined.
>
>
>> Ok, so what do you do for gate outputs then, Andre?
>>
>> The schematic I'd got was exactly what you describe - Op-amp, bit of gain,
>> 1K resistor in series with the output.
>>
>> But I'm open to better ideas.
>
>
> Hi Tom,
>
> Use the opamp, but put the current-limiting/protection resistor inside the
> feedback loop (think this was discussed recently in another thread). Then
> the output remains constant with varying load (within reason) but the
> driving device is still protected.

And add a little capacitor between the output pin and the -ve input to
stabilise the loop w.r.t. input capacitance.

http://www.analog.com/library/analogDialogue/archives/39-05/Web_Ch7_final_J.pdf

Page 80, ignore the diodes and concentrate on Cf, Rf, Rout1 and Rout2.

Cheers,
Neil
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