[sdiy] Nice info on decoupling caps

[Harry Bissell]

power supply planes on the outer layers are a double edged sword...

the planes on the outside can shield stray emissions (either direction)

downside, 
the inductance between the V+ and V- planes is larger (they are further apart)
You can't easily access signals unless you were very clever with test points
circuit modifications are very difficult

also

SMT layouts are more efficient with traces on the outer layers (in effect, two single sided
boards laminated atop the power planes...

Each method has its uses. especially for very high speed CPU bus signals, burying the traces
internally can really help out on passing emitted noise tests

You points about power supply inductance are excellent !  on double sided boards, I run the power supply
traces parallel to each other under the ICs to minimize loop area.

H^) harry



----- Original Message -----
From: Richie Burnett <rburnett at richieburnett.co.uk>
To: synth-diy at dropmix.xs4all.nl
Sent: Thu, 19 Jan 2012 18:34:01 -0500 (EST)
Subject: Re: [sdiy] Nice info on decoupling caps

When planning supply rail decoupling on a PCB it is often inductance in the 
supply wiring that is more troublesome than resistance.  After all, you can 
minimise resistance by using progressively wider copper traces or thicker 
copper weight, but both of these changes do little to reduce self inductance 
in the current path.

Power supply stray inductance is particularly apparent where rapidly 
changing current draws are encountered.  (By rapidly changing I mean going 
from one value to the other in a short time [high di/dt], rather than 
something that is necessarily oscillating at some high frequency but might 
vary smoothly.)  Voltage developed across an inductor is equal to L times 
di/dt.  So if the current changes abruptly enough it will generate a large 
voltage spike across stray inductance anywhere in the current's path!  If 
there happens to be significant stray inductance in the supply wiring then 
all devices connected at that point will see large voltage spikes due to L 
di/dt whenever the load current changes abruptly.

This is a classic problem for digital circuits as they frequently draw large 
current pulses as their transistors switch from one logic state to the other 
passing through the linear region.  The solution is to place decoupling 
capacitors locally to all devices that exhibit high di/dt.  The local 
capacitance stiffens the supply and helps to absorb the packets of energy 
stored up in supply wiring inductance.  Design engineers frequently place 
100nF 0805 multi-layer SMD caps across every other IC in digital systems 
simply because they are dirt cheap in the hundreds of thousands, and it is 
much cheaper than a product recall and rework excercise if they are found to 
be necessary at a later date.  The reason why they have to be placed *right* 
up next to the IC?  To minimise stray inductance.

You can also go a long way to minimising stray inducance in supply wiring by 
making sure the V+ and V- wires take as closely as possible the same routes. 
(It is "enclosed area" that makes for lots of inductance, so if you minimise 
the area between the V+ and V- wires you minimise the inductance.)  For 
example, you can twist together the red and black wires coming from the 
power supply to keep them as close together as possible, then you could use 
power planes on two layers of your PCB to take power "to" and "from" each 
part that requires it.  This close placement of the two supply nets 
miminises inductance and also builds in some distributed decoupling 
capacitance.

On a 4 layer board the V+ and V- rails can take the outer two layers, with 
all high speed signals on the internal two layers.  This makes a PCB with 
very low supply inductance, and minimal RF radiation or susceptibility 
because the power planes on either side screen the internal signals from the 
outside world.  For a mixed analogue and digital PCB these layers can carry 
Analogue V+ and V- in one area of the board and Digital V+ and V- in 
another, and shouldn't overlap.  Such a layout goes a long way to ensuring 
that any voltage spikes on the supply rails due to high di/dt in the digital 
circuit don't make it into the sensitive analogue parts.

Hopefully some useful info on the decoupling and RF susceptibility thread,

-Richie Burnett, 

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-- 
Harry Bissell & Nora Abdullah 4eva