[sdiy] Fast envelope generation
tom at electricdruid.net
Tue Dec 18 16:14:00 CET 2012
On 18 Dec 2012, at 13:44, Scott Gravenhorst wrote:
> When I've needed an exponential response for an envelope, I've used a single pole
> lowpass IIR filt. So far, I've used this only for the release phase of an ADSR, but it
> works very nicely (in an FPGA) and I've not had a problem with it's computational expense.
> BUT - perhaps I don't understand what you are doing? Or am I confusing logarithmic and
No, I don't think there's any confusion, but my bet is you're both on platforms with nice wide number formats. Scott's on FPGA, and can make his variables as wide as he wants - 32, 48-bits, whatever - and I bet he does.
The trouble with doing IIR on a little 8-bit uP is maintaining accuracy. If you use long multi-byte variables, you finish up needing to do long multi-byte multiplications - slow, especially on a PIC with no multiply instruction. If you *don't* use long variables, the accuracy goes to pot.
At one point I looked into IIR for this job, and I needed better than 32-bit to get the range of delay times I needed. Though the calculation is "simple", it finished up needing more lines of code for the multiply than the simple table-lookup-with-interp. The advantage of that method is that you can easily change the times and the curves shapes without any worries about the accuracy.
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