[sdiy] Variable rate waveform playback in NED synclavier
dmarv at dop.com
Fri Aug 31 20:16:32 CEST 2012
On 8/31/2012 7:25 AM, Tom Wiltshire wrote:
> Going back to the voice diagram:
> There's one bit I don't understand. On the left hand side of the diagram are the two Sample Rate Generators, which seem to take a clock signal Fclk and multiply it by a fraction N/M, where N and M are 8-bit numbers. How is this done? Doing arbitrary division is easy enough (just count M clock pulses) but how is the multiplication performed? Would it have to be a PLL with a divider in the feedback loop? This seems a bit dirty for NED. If not, how? I can't see how this bit works.
> Secondly, once this new sample rate is generated from the Fclk, it's fed to a Phase Angle Incrementer, which I take it is what we'd call an NCO. This seems to have a 8-bit frequency increment. So the final frequency is some weird combination of the variable sample rate Fclk*N/M and the freq inc - does this seem right or am I miles off here?
Go to this site <http://www.pat2pdf.org/> and look up Patent 4554855.
This Flicker site has a large collection of high resolution pictures of
many NED Boards:
Lots of virtual reverse engineering here ...
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