[sdiy] Weird MFOS VCO max CV problem

[Tim Stinchcombe]

> >Well I've been looking at that schematic and wondering whether I'm 
> >reading it right, or if there is a mistake in it: I see nothing at 
> >comparator U2-B output, pin 7, to stop the gate of Q1 going so high 
> >that the gate-to-channel becomes forward-biased, other than 
> the rate at 
> >which the main integrator cap C6 discharges, thus taking the 
> comparator 
> >low again. At low frequencies/small currents sunk by U3 pin 
> 1, I doubt 
> >this is a problem, but as the current increases, simulation suggests 
> >that the gate can go way positive, so it starts dumping loads of 
> >current into the channel. This then appears to give a feedback loop 
> >into the comparator, so is it possible that rather than the 
> oscillator 
> >stopping, that U2-B is bursting into oscillation at MHz/whatever?
> 
> Why wouldn't your arguement apply to the original TM design 
> and its many 
> successful variations?

It would, the implication being that actually it is rather a piss-poor
argument (rather too much like 'thinking aloud', though at least there were
a smattering of question marks to indicate my uncertainty). If 'TM' is Terry
Mikulic, then what looks like an earlier version of the circuit in
Electronotes 62 has a slightly different arrangement, using an LM311
comparator rather than an op amp, which would lessen (and likely completely
rule out) the possibility of forward-biasing the JFET (not that that is
necessarily a problem).

In any case, I have more or less answered my own questions:

> Am I missing something?

A few things, clearly! Quite of lot of current gets through the gate due to
capacitive coupling, and since this doesn't cause a major problem, it
doesn't necessarily follow that forward biasing the gate would be a big
problem either.

> What is the purpose of diode D8? Is 
> it supposed to clamp the gate to ground?

It only has a miniscule effect that I can see (in calculations and
simulations at least). It increases the lower switching threshold of the
comparator (from around 25mV - ish - without, to about 480mV with), making
the JFET turn off sooner at the end of the reset pulse. But since the rate
of discharge of the cap is apparently so much faster than the slew rate of
the op amp, the cap gets fully discharged in any case, so the ramp output
slams down close to ground regardless.

> Is R50 coming off 
> the wrong place...?)

The VCO could probably still be made to work if R50 _were_ taken off D8
anode, but the output voltage swing would be less (less time for the
discharge), and there may then be problems with individual JFET threshold
voltages being too low, causing it to not be turned off completely (so the
answer is very probably 'no').

None of which of course helps with the OPs original problem, though I do
note that the currents at the integrator are teeny-tiny even for the top end
of the audio range, e.g. 10kHz only requires approx 10uA, and yet the expo
converter is capable of outputting currents that are  orders of magnitude
greater, maxing out somewhere around 900uA or so - simulation gives this to
be around 300kHz, and it is starting to get quite out of shape - i.e. _way_
above what is audible...

Tim
__________________________________________________________
Tim Stinchcombe 

Cheltenham, Glos, UK
email: tim102 at timstinchcombe.co.uk
www.timstinchcombe.co.uk