[sdiy] Weird MFOS VCO max CV problem

[Ian Fritz]

At 04:40 PM 4/11/2012, Tim Stinchcombe wrote:


>Well I've been looking at that schematic and wondering whether I'm reading
>it right, or if there is a mistake in it: I see nothing at comparator U2-B
>output, pin 7, to stop the gate of Q1 going so high that the gate-to-channel
>becomes forward-biased, other than the rate at which the main integrator cap
>C6 discharges, thus taking the comparator low again. At low
>frequencies/small currents sunk by U3 pin 1, I doubt this is a problem, but
>as the current increases, simulation suggests that the gate can go way
>positive, so it starts dumping loads of current into the channel. This then
>appears to give a feedback loop into the comparator, so is it possible that
>rather than the oscillator stopping, that U2-B is bursting into oscillation
>at MHz/whatever?

Why wouldn't your arguement apply to the original TM design and its many 
successful variations?

   Ian