[sdiy] SMD experiences

[Tom Wiltshire]

On 9 Sep 2011, at 08:03, Dave Manley wrote:

> On 9/8/2011 11:08 PM, Matthew Smith wrote:
>> Quoth David G Dixon at 09/09/11 11:15...
>>> I would say, just watch out for capacitive and inductive effects,
>>> particularly with long high-impedance traces running in parallel with signal
>>> traces. With 4-layer boards, layer-to-layer bleedthrough may become and
>>> issue if traces are parallel.
>> 
>> For the purposes of what I'm doing, the first copper layer below the top is a ground plane (and I mean plane - all filled, except where there are vias,) the second being a power plane.
>> 
>> If I end up with any long signal traces, my board is too big ;-)
>> 
>> As regards stability caps, that's easy to factor into the design - I've already got power decoupling caps all over the shop, adding these to the design procedure just involves me writing a PostIt note
>> to get me to remember to check all schematics to ensure feedback circuits have them. Think I should have no shortage of 22pF 0603s - that's what the clock crystal loading caps are on most of my
>> microcontrollers.
>> 
>> If you look at the BOM for my ADSR/LFO, the vast bulk of the components are either decoupling caps or filter caps for the ADC inputs - stability caps on what few analogue parts there are will be in
>> good company.
>> 
>> But 4-layer is there if I need it. Just a case of balancing the $10 per square inch against $5 per square inch, and the fact that I'll have the inconvenience of turning layers off in Eagle so that I
>> can see where I am routing the middle layers ;-)
>> 
>> 
> Probably covered already, but if not: make sure to add thermal relief pads to any
> thru-hole components that connect to the planes.

What's a "thermal relief pad" and why would I only need one for through-hole?

I'm enjoying this thread. I'm still yet to go over to the tiny side of the force, but it's power is strong.

T.