[sdiy] FPGA

[James Elliott]

Yea, I guess my initial post was a "little" nebulous. I sent that email in desperation after many many hours of reading about AVRs & FPGAs, specifically about how to integrate them with SDRAM. I was looking at the 32bit AVRs and the Spartan 3 FPGAs (I even spent a bit of time reading about the Parallax Propeller - I don't know that I want to waste time learning a one-shot language though).


As far as requirements are concerned I want to build a two voice (at least) 16 or 24 bit sampler with a sampling rate of at least 44.1khz.I've already built 2 WTPA samplers, but quite frankly I don't like them that much. Their noise floor problems renders them almost useless for my needs. I understand a completely new version is going to be released in the near future (I've been following the discussions since it was first mentioned); however, I really want to learn how to program embedded devices and I figured I would *try* to kill 2 birds with one stone. My biggest concern at this point is not necessarily in the programming but in actually building a a complete "system", that is FPGA, clock, ADC, DAC, inputs, outputs, memory. I have plenty of programming experience, just not with embedded devices (outside of schoolwork & a couple basic PIC programs for work work)...

Scott G, what Spartan 3 starter kit are you using and how did you incorporate the ADC, DAC, and DDR SDRAM? Were those already on the board or did you have to design your own circuit?? If you had to design your own circuit, what devices did you use and do you have any pointers (no pun intended)?

-Jim



----- Original Message -----
From: Scott Gravenhorst <music.maker at gte.net>
To: synth-diy at dropmix.xs4all.nl
Cc: 
Sent: Thursday, October 27, 2011 6:49 AM
Subject: Re: [sdiy] FPGA


Eric Brombaugh <ebrombaugh1 at cox.net> wrote:
>Of course it's feasible for some set of system specs 
>(cost/complexity/sample length/sample rate/etc). What are your 
>requirements? Scott Gravenhorst has been doing some work on 
>SDRAM-based deep memory buffers using the Spartan 3E starter kit 
>which would allow some fairly complex sampling. More than you're 
>likely to get with any AVR out there at least. 
>
>Eric
>
>On Oct 26, 2011, at 9:22 PM, James Elliott wrote:
>
>> Would it be feasible to build a sampler with a FPGA? Or should 
>I go AVR or ARM?????????????????????????? 

I'm '' this close to a test of a looped delay effect using the DDR
SDRAM on the Spartan-3E Starter Kit using an already developed FM bell
synth as an audio source.  If I were to use the full RAM, several
minutes of mono delay is possible (at the sample rate of about 65 kHz).
This would mean several minutes of sample time on a sampler as well.

In fact, the project that I used as a basis for my own was done by Rick
Huang.  It is called the "widebus recorder" and is a sampler and
playback design.  So it's really right there in his project.  All that
is needed is an anti-alias filter on the input to the ADC.  I'm not
sure why (but I may be about to find out) other than for longer record
time, but Rick's design runs at a sample rate of 40 kHz.  I found the
zip with Verilog source code using google.


-- ScottG
________________________________________________________________________
-- Scott Gravenhorst
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