[sdiy] FPGA

[Scott Gravenhorst]

Eric Brombaugh <ebrombaugh1 at cox.net> wrote:
>Of course it's feasible for some set of system specs 
>(cost/complexity/sample length/sample rate/etc). What are your 
>requirements? Scott Gravenhorst has been doing some work on 
>SDRAM-based deep memory buffers using the Spartan 3E starter kit 
>which would allow some fairly complex sampling. More than you're 
>likely to get with any AVR out there at least. 
>
>Eric
>
>On Oct 26, 2011, at 9:22 PM, James Elliott wrote:
>
>> Would it be feasible to build a sampler with a FPGA? Or should 
>I go AVR or ARM?????????????????????????? 

I'm '' this close to a test of a looped delay effect using the DDR
SDRAM on the Spartan-3E Starter Kit using an already developed FM bell
synth as an audio source.  If I were to use the full RAM, several
minutes of mono delay is possible (at the sample rate of about 65 kHz).
 This would mean several minutes of sample time on a sampler as well.

In fact, the project that I used as a basis for my own was done by Rick
Huang.  It is called the "widebus recorder" and is a sampler and
playback design.  So it's really right there in his project.  All that
is needed is an anti-alias filter on the input to the ADC.  I'm not
sure why (but I may be about to find out) other than for longer record
time, but Rick's design runs at a sample rate of 40 kHz.  I found the
zip with Verilog source code using google.


-- ScottG
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