[sdiy] Spartan-3E Starter Kit DDR SDRAM Demo

[Scott Gravenhorst]

For anyone here who owns a Spartan-3E Starter Kit (and is not a member of FPGA-Synth), I
have completed a "hello world" design that uses the on board 64 megabyte DDR SDRAM.

The project started with Rick Huang's widebus recorder project (an audio record and
playback project).  I modified the main state machine to prove to myself that I understand
the interface.

http://jovianpyx.dyndns.org:8080/public/FPGA_synth/SDRAM_hello_world.zip

Just source code.  Nothing special about the project settings.  I'm using
WebPACK ISE ver. 13.1

Most of the code is Rick's.  I've replaced one of his state machines with
my own (in ctrl_FSM.v).  I've reformatted the text to be more visually
pleasing to me and I've added comments to what Rick put there.

When first started, the LED readout will probably be incorrect.  This is
because it needs to be reset (I didn't take the time to write an automatic
startup reset cycle).  To perform a reset for this project, do this:

Press and hold down the rotary encoder pushbutton.
Press the south pushbutton and release it.
Relase the rotary encoder pushbutton.

A correct result will display one illuminated LED starting with the right
side.  The illumination shifts left every 0.25 seconds.  When the last LED
is illuminated, the process starts over and goes forever.

-- ScottG
________________________________________________________________________
-- Scott Gravenhorst
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