[sdiy] LAG circuit de-tuning VCO question

[Tom Wiltshire]

On 5 Nov 2011, at 13:20, Tom Wiltshire wrote:

> 
> On 5 Nov 2011, at 12:39, Neil Johnson wrote:
> 
>> Tom Wiltshire wrote:
>>> Wouldn't the series resistance of the capacitor have an effect in
>>> this circuit too? It'd effectively make the lower end of a potential
>>> divider. I'd have thought you'd do better with caps with low ESR.
>> 
>> Errr.. no.  ESR is only significant in low-impedance AC circuits, and this is a high-impedance DC circuit.  Completely not applicable.
>> 
>> In the DC steady state that is causing Dave problems its the leakage current through the electrolytic that gave rise to an undesirable voltage drop across the 1M0 pot.
>> 
>> Neil
> 
> Fair enough. Is there no series resistance at DC at all, then?
> 
> Tom

Let me rephrase that - the series resistance at DC should be infinite, right? Hence no leakage.

Tom