[sdiy] LAG circuit de-tuning VCO question

[Tom Wiltshire]

Wouldn't the series resistance of the capacitor have an effect in this circuit too? It'd effectively make the lower end of a potential divider.
I'd have thought you'd do better with caps with low ESR.

T.

On 5 Nov 2011, at 00:42, Dave Kendall wrote:

> Hey Oren - many thanks  - I reckon you've solved it :-)
> 
> I swapped out the aluminium electrolytic for a wima poly cap of 680nF, and a 1uF poly box cap (rapid own brand) and both worked fine - no problem!
> I would never have suspected the difference would be so dramatic - either alu electros are simply not good enough,  or maybe I have a bad batch...
> 
> Thanks again!
> 
> cheers,
> Dave
> (I love this list ;-)
> 
> 
> 
> On Nov 5, 2011, at 00:18, Oren Leavitt wrote:
> 
>> 
>> 
>> On 11/4/2011 6:28 PM, Dave Kendall wrote:
>>> Hi All.
>>> 
>>> I have a playing with a simple expo lag circuit consisting of;
>>> 
>>> 1V/octave input to an op amp wired as unity gain voltage follower, the
>>> output of which goes through a 1M Linear pot wired as variable resistor,
>>> then into a second voltage follower with a 1uF cap to GND at its input.
>>> I notice that without even changing the input CV, setting the pot to max
>>> de-tunes the output by up to several 100 cents, judging by ear.
>>> 
>>> The effect is more pronounced the higher the input CV - around 0V to 1V
>>> input, it's hardly noticeable.
>>> 
>>> Is this normal, and is there a way to remove the effect? it makes it
>>> pretty useless for accurate VCO use. One can mitigate the effect a bit
>>> using smaller resistors/caps, but then the lag time is very short.
>>> 
>>> Any ideas anyone?
>>> 
>>> cheers,
>>> Dave
>>> 
>> 
>> Capacitor leakage - maybe?
>> 
>> - Oren
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