[sdiy] 2164 Expo correction

[Jerry Gray-Eskue]

<< Anyway, based on the numbers I measured, I found that I could model the
exponential response (which should be linear on a log-linear plot) more or
less perfectly with a quadratic function.>>

This may be correct but I would suggest checking the measurements with other
2164s to make sure this is typical of the parts and review your current Expo
section to be sure it is not introducing math functions that are clouding
the issue.

-----Original Message-----
From: synth-diy-bounces at dropmix.xs4all.nl
[mailto:synth-diy-bounces at dropmix.xs4all.nl] On Behalf Of David G. Dixon
Sent: Friday, March 25, 2011 5:22 PM
To: 'Synth DIY'
Subject: [sdiy] 2164 Expo correction

Hey Team,

As you know from my previous ramblings in this forum, the log conformance of
2164 leaves a fair bit to be desired, which is really the only thing
detracting from its use as an expo converter.

Lastnight I measured the frequency from my latest 2164 Expo VCO prototype (a
tri-square core with LM311 comparator reset) as a function of the voltage
applied at the current-sourcing VCA's VC pin.  I set the frequency to exact
powers of 2 (i.e., 8, 16, 32Hz, etc, all the way up to 4096Hz) and measured
the voltage at the VC pin with a DVM to the nearest mV.  For the particular
2164 chip I measured, the exponential response (ignoring any delay effect of
the comparator reset) was roughly 180mV per octave at the bottom of the
audio range (at about VC = 1470mV), and increased to roughly 190mV per
octave at the top of the range (at about VC = -360mV).  This is in contrast
to the constant 200mV per octave one would expect from the stated 33mV/dB of
the datasheet.  The fact that the gain is not constant is the direct
manifestation of the poor log conformance of 2164.

Anyway, based on the numbers I measured, I found that I could model the
exponential response (which should be linear on a log-linear plot) more or
less perfectly with a quadratic function.  It turns out that a diode (or
diode-connected transistor), even one suitably biased, is totally
inappropriate for correcting this tracking error, even though it should be
perfect for correcting the tracking error associated with integrator reset
delays.

However, based on the quadratic response, I tried replacing the Ebers-Moll
model of a BJT with the square-law model of a JFET, and it would appear that
a JFET is perfect.  Now my quandary is that it looks like I'll need both the
JFET and a BJT (each with its own biased, inverting, gate-driving opamp)
sending separate currents back to the CV summer to completely correct the
tracking of VCOs with 2164 expo converters.

Has anyone else gotten up to similar mischief?

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