[sdiy] DIY Parallel DAC

[Noah Vawter]

On Jul 31, 2011, at 2:42 AM, Veronica Merryfield wrote:
> To the resistor precision question, it boils down to the network  
> error being less than one bit, or rather, less than half a bit.  
> There is a lot more to it, but that would get you pretty close. So a  
> 0.1% resistor network would probably be good to 9-bit (1 in 512)  
> with a simplistic analysis. But, and it is a big one, there are a  
> lot of issues that need to be considered... is the variation in the  
> logic level output at or less than 0.1%? Do you need a different  
> reference scheme, and if so, is the switch differences at or less  
> than 0.1%, how do cumulative 0.1% errors combine (worst and best  
> case), what does the non0linearity look like for that, and so on.


Since it's an FPGA, maybe use an 8-bit DAC with sigma-Delta inside the  
FPGA to increase to 12+?  it wouldn't take as much internal real- 
estate as a one-bit DAC.

Also, even though it's non-conventional, I like the idea of using an  
FPGA combine some of the commonly-used modules!  Although I would  
prefer a CPLD.





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