[sdiy] DIY Parallel DAC

[Simon Brouwer]

Hi Matthew,



Matthew Smith schreef:
> Hi Folks
>
> Due to the lack of sensibly-priced parallel load DACs (and the fact I
> don't want to muck around with serial timing for waveform generation) I
> am looking to drive a R-2R ladder DAC directly from an FPGA.
>
> Other than buffering the output and using half-decent resistors (looking
> at some Vishay 0.1% at $1.52 a piece, in easy-to-solder 0805 packages)
> is there anything I should be aware of? (And can I get away with lower
> precision/cheaper resistors?)
>
> Working on a 3.3V reference, 1k and 2k resistors.
>
> For those who are curious:
>
> This is actually a Next Generation of the wavetable design I'm playing
> with at the moment. Whilst I'm trying to use "legacy" parts in the first
> design (venerable 8-bit DAC, EPROMs,) the complexity of the decoding
> logic required drove me to use a CPLD to generate ROM addresses from the
> incoming clock signal.
>
> The FPGA design crams all of what I have conceived so far into a single
> part - MIDI note, wave select, sub-octave select (I'm using 3 ROMs+DACs
> per voice, octave and wave individually selectable) - input is an I2C or
> SPI message, output is the logic driving the resistor ladder.
>
> Cheers
>
> M
> --
> Matthew Smith

You can drive an R/2R ladder from a CMOS buffer or a register such as
74HCT377. Make sure the IC has its own well decoupled/stabilized voltage
rail and use large resistors (50..100k or so) to minimize the influence of
the output resistances which can be up to ca. 70 ohms. With some 0.1%
resistors for the most significant bits you could get around 8 bit
accuracy.

-- 
Vriendelijke groet,

Simon Brouwer
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