[sdiy] DIY Parallel DAC

[Paul Maddox]

Silly question, Why are you clocking the DAC at all?

why not just put the data on the output lines and leave the DAC
constantly updating? it's what I did in the monowave. IMHO, the only
time you "clock" a DAC is when you can't guarantee the bits will
arrive at the parallel in at the same time.

Paul

On 31 July 2011 12:49, Matthew Smith <matt at smiffytech.com> wrote:
> One of the reasons I wanted to go the DIY DAC route was to learn - I believe
> that to truly understand something, I need to build it from scratch.
>
> For all your responses, I am truly grateful. That's a LOT of information and
> ideas - I'll attempt a synthesis (ha!) over the next couple of days.
>
> Now to address the various questions/comments, in no particular order:
>
> * Why am I looking for a parallel solution?  Because my original design is a
> clock driving a counter that drives the address lines of an EPROM, the data
> from which drives a DAC.  The evolution of this is to replace the EPROM with
> a lookup table in the FPGA, this driving the DAC. With FPGAs, you can have
> arbitrary data widths - no having to send 12 bits as 2 x 8-bit words.  If I
> want a 12-bit DAC, I just have 12-bit outputs from my lookup tables, and
> present these to the output pins. Pure simplicity.
>
> * Why not serial? I am using 1024 bit samples, clocked at the appropriate
> rate for the frequency required. Nearly all the serial DACs from my regular
> vendor (Element14) seem to rely on SPI for timing. I like to treat SPI as
> asynchronous, when dealing with microcontrollers. Send stuff out fast, but
> allow other tasks (from interrupts) to take priority. Resetting the SCK rate
> all the time also lacks charm.
>
> Having said that, I have put an SPI DAC into my ADSR design - can't remember
> the part number, but it's a Microchip device which has a load pin so that
> conversion can be timed precisely, but still with an asynchronous SPI.
>
> [Aside: I have avoided SPI up until very recently as I simply hadn't used it
> before. All my microcontroller work has been very simple, all communications
> being via U(S)ART. Tried to use SPI from an ATTiny2313 to control an
> LTC6903, which I am trialling for clock generation for Mark I wavetable
> system. Had so many problems with the restrictive implementation that I
> ended up having to big-bang the SPI rather than use the integrated
> peripheral. Worked like a charm :-)  Now that I "get" SPI, working on my
> own, simple, Verilog implementations in CPLDs.]
>
> But I think Veronica has answered my issue with changing SCK rates - put the
> value in a register and push samples out at a fixed rate. With the
> parallelism you can get from programmable logic, this should work well -
> just need to push it out sufficiently fast that no jitter occurs from the
> timing of register updates versus SPI transmissions.
>
> * Which parallel DACs have I looked at? Not many - either Element14's search
> isn't up to much (I've had issues finding stuff before,) or they have
> limited lines. The reason I'm only searching on this vendor is that I have
> to get the stuff from somewhere. Digikey & Mouser are out of the question,
> as they have arm-and-a-leg freight for anything under $200.
>
> * Picked resistors - yes, this is a one-off. It's a "how does it work" and a
> "because I can." Whilst I like to work with SMD devices, as it keeps PCBs
> small (and cheap) I do have a box of 1,000 1k ex-military resistors. I think
> I may well do some measurements and build a ladder on matrix board. I only
> have the one value, but then I can match pairs for series resistance for the
> 2R part.  As far as I can make out, it's the MSB end that is most critical
> on values.
>
> I would not consider using home-brew DACs in a commercial product unless it
> were the audiophile market - in which case I'd buy the cheapest Chinese
> resistors on eBay, dip them in gold paint mixed with snake oil, and sell for
> $2k a piece ;-)
>
> * Variation in output levels - interesting point. I've got a Spartan 3E demo
> board - think I'll set it up to pull a load of pins high, dump a load on
> them and measure the voltage, just to see what sort of variance   I get.
>
> * For the purposes of what I was looking to achieve, I will probably go with
> an SPI DAC, as the parallelism of an FPGA and Veronica's observation should
> mean that it will work just fine. HOWEVER, I still want to build a discrete
> DAC and, since this is for the sake of doing it, will take up Dave's
> suggestion and attack my box of 1k resistors and see what I can put
> together.
>
> * I will read through Robin's notes on the Casio DACs with great care. I
> knew there had to be prior art I could use for inspiration :-)
>
> Thanks again, all. Your input is really appreciated.
>
> Cheers
>
> M
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