[sdiy] DIY Parallel DAC for audio signals, especially at x00kHz sample rates

[Robin Whittle]

Hi Matthew,

Here are some thoughts based on building high-fidelity audio DACs
without any sample and hold arrangements.  This is based on the Casio
931 chip series:

  http://www.firstpr.com.au/rwi/casio/

These put out a 14 bit value with a sample rate of 567.086kHz.  The
original circuit was to put the LSI chip's outputs into some inverters,
and then into the R-2R network, with the MSB and I think the 2nd MSB
resistors driven by multiple buffers in parallel.  There was no sample
and hold, because the very high sample rate was faster than the settling
time of the resistor network, with its resistances and capacitances.

You can get SIP packaged 8 bit R-2R networks which are laser-trimmed to
high precision.  I think Bourns make them.  Achim (ASSI) wrote to the
list with URLs for these and other brands.

Casio used some obscure brand which I recall was a 10 bit R-2R network,
with the last two to four bits being done with discrete resistors.  On
some instruments - maybe only the M10 - I recall they only used 12 of
the 14 bits.

The stability and noise-free nature of the buffer's supply is important,
of course.

The impedance of the buffer driving the resistors becomes significant
for the MSB and probably the 2nd Most Significant Bit.  The MSB is the
real worry, since it is transitioning right in the middle of the audio
voltage range.  So as sounds die away exponentially, there is a glitch
from any MSB weighting error which persists until the signal no longer
goes below 0.  This can be reduced by adding a constant to the digital
signal before output, to drive its zero level somewhat numerically above
actual zero.  That would reduce the available range in the positive
direction, but there would be no MSB glitches once the volume was below
a certain level.

The impedance of the buffers is not necessarily the same for positive
output as for negative.

The fix for both of these is to run multiple buffers in parallel for the
MSB and probably the 2nd MSB.  However, in fact, you don't really need
to make the MSB perfect, since there will be errors anyway which you
need to trim out.

The timing of the rise and fall times of the LSI chip (FPGA in your
case) is not necessarily symmetrical for rising and falling signals.
Even if it was, then ordinary buffers are not necessarily going to
respond with the same time delay.

I think the best fix for this is to use an edge-triggered latch instead
of the inverter or non-inverting ordinary buffers.  With a sufficiently
fast one of these, the rise and fall times from the clock edge will be
close enough to equal not to be a problem.  With enough of these in
parallel for the MSB, you will reduce the MSB DC error, and with the
equal rise and fall times you won't get much in the way of glitches.

Without this - with any significant difference between rise and fall
times - you will get nasty spikes.

Consider the transition between zero and minus 1:

  1000 0000
  0111 1111

If the rise time is less then the fall time, then there will be a brief
time, perhaps only fractions of a nanosecond, in which the output will
be 0000 0000, which results in a highly audible spike at every
transition of the audio signal to below zero.

Even if you get all this right, including some theoretically massive
number of latch outputs in parallel for the MSB, then there will be two
sources of trouble.  (BTW, the R-2R network goes to a ground summing
point of an op-amp, not into a voltage follower op-amp - so the R-2R
network is functioning as a current source.)

Firstly, your MSB resistor will probably not be providing exactly
128/127 of the current of all the other resistors.  So there will be a
non-linearity just below zero.   The solution to this is a trimpot
taking a small fraction of the MSB voltage, and its inverse, via a
resistor, to the op-amp summing point input.

If you look at the PDF from the above page, on page 13, Fig 9 shows
Casio's circuit.  They don't even parallel the buffers for the MSB drive
to the R-2R network.

Casio's MSB trimpot is driven on one side by its own MSB buffer and on
the other from an inverting buffer running from this.  So there is going
to be a propagation delay in the second buffer giving a big, brief,
spike at MSB transitions where briefly both ends of the trimpot go to
ground, or both go high.  It's only a 10M trimpot, but still, via
resistance and capacitance, there's a glitch.   So I think the trimpot
should be between the outputs of two latches.  One is driven from your
FPGA MSB output and the other is driven from the inverse of this.  This
way, both latches will change state at the same time.

Even then, you will be up against the different capacitances of the
inputs to the R-2R network and the output which goes to the op-amp.

The only way to fix this is to devise some very small capacitive
coupling of a positive or negative version of the MSB signal to the
op-amp input, which you already have for the MSB adjustment trimpot as
just described.

I think two wires sticking up above the PCB, bent towards each other, is
probably enough to give the required capacitance, depending on how you
wire up the R-2R network.  Ideally, you would put a ring around the
output terminal of the R-2R network, at the end of the SIP package, to
capacitively protect it from the next pin which is the MSB input.

With the Casio machines, I built or modified a handful to have 74HC174
latches and careful trimpot and capacitive glitch correction - and to
bypass the analogue filter which lowered the top-end frequency response.
 They can sound really good, especially with their sharp geometric
waveforms and almost no aliasing due to the extraordinarily high sample
rate.

If your project is only doing ordinary audio sampling rates, I think it
might be easier to use conventional DACs, which can settle in a few
microseconds.  However, to do these half MHz sample rates, you will
surely run into DC and capacitive glitches with almost any DAC.  By
rolling your own like this, you will be able to null out both the DC
trim glitch and the capacitive glitch, which won't necessarily be
possible with a serial in IC DAC.


The PDF reproduction of the document I made about the M10 and MT31
(primarily) is at the above page.  Its nearly 31 years since the M10 was
released (late 1980 in Australia).  The birth of portable, polyphonic,
digital musical instruments!  Look back another 31 years and the
transistor had barely been invented.

 - Robin


On 31/07/2011 3:23 PM, Matthew Smith wrote:

> Hi Folks
> 
> Due to the lack of sensibly-priced parallel load DACs (and the fact I
> don't want to muck around with serial timing for waveform generation) I
> am looking to drive a R-2R ladder DAC directly from an FPGA.

 . . .